Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B520F2048IQ100 /PRS /CH21_CTRL

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Interpret as CH21_CTRL

SOURCESEL=NONE, EDSEL=OFF

Description

Channel Control Register

Fields

SIGSEL	Signal Select
SOURCESEL	Source Select 0 (NONE): No source selected 1 (PRSL): Peripheral Reflex System 2 (PRS): Peripheral Reflex System 3 (PRSH): Peripheral Reflex System 4 (ACMP0): Analog Comparator 0 5 (ACMP1): Analog Comparator 1 6 (ADC0): Analog to Digital Converter 0 7 (RTC): Real-Time Counter 8 (RTCC): Real-Time Counter and Calendar 9 (GPIOL): General purpose Input/Output 10 (GPIOH): General purpose Input/Output 11 (LETIMER0): Low Energy Timer 0 12 (LETIMER1): Low Energy Timer 1 13 (PCNT0): Pulse Counter 0 14 (PCNT1): Pulse Counter 1 15 (PCNT2): Pulse Counter 2 16 (CRYOTIMER): CRYOTIMER 17 (CMU): Clock Management Unit 23 (VDAC0): Digital to Analog Converter 0 24 (LESENSEL): Low Energy Sensor Interface 25 (LESENSEH): Low Energy Sensor Interface 26 (LESENSED): Low Energy Sensor Interface 27 (LESENSE): Low Energy Sensor Interface 28 (ACMP2): Analog Comparator 1 29 (ACMP3): Analog Comparator 3 30 (ADC1): Analog to Digital Converter 0 48 (USART0): Universal Synchronous/Asynchronous Receiver/Transmitter 0 49 (USART1): Universal Synchronous/Asynchronous Receiver/Transmitter 1 50 (USART2): Universal Synchronous/Asynchronous Receiver/Transmitter 2 51 (USART3): Universal Synchronous/Asynchronous Receiver/Transmitter 3 52 (USART4): Universal Synchronous/Asynchronous Receiver/Transmitter 4 53 (USART5): Universal Synchronous/Asynchronous Receiver/Transmitter 5 54 (UART0): Universal Asynchronous Receiver/Transmitter 0 55 (UART1): Universal Asynchronous Receiver/Transmitter 1 60 (TIMER0): Timer 0 61 (TIMER1): Timer 1 62 (TIMER2): Timer 2 67 (CM4): undefined 80 (TIMER3): Timer 3 82 (WTIMER0): Wide Timer 0 83 (WTIMER1): Wide Timer 0 84 (WTIMER2): Wide Timer 2 85 (WTIMER3): Wide Timer 3 98 (TIMER4): Timer 4 99 (TIMER5): Timer 5 100 (TIMER6): Timer 6
EDSEL	Edge Detect Select 0 (OFF): Signal is left as it is 1 (POSEDGE): A one HFCLK cycle pulse is generated for every positive edge of the incoming signal 2 (NEGEDGE): A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal 3 (BOTHEDGES): A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
STRETCH	Stretch Channel Output
INV	Invert Channel
ORPREV	Or Previous
ANDNEXT	And Next
ASYNC	Asynchronous Reflex

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